... | ... | @@ -43,24 +43,24 @@ CPU が一通り完成したら、その上でプログラムを動かすこと |
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```verilog
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module cpu_tb;
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reg clk;
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reg rst_n;
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reg sysclk;
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reg cpu_resetn;
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wire uart_tx;
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parameter CYCLE = 100;
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always #(CYCLE/2) clk = ~clk;
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always #(CYCLE/2) sysclk; = ~sysclk;;
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cpu cpu0(
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.clk(clk),
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.rst_n(rst_n),
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.sysclk;(sysclk;),
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.cpu_resetn(cpu_resetn),
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.uart_tx(uart_tx)
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);
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initial begin
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#10 clk = 1'd0;
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rst_n = 1'd0;
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#(CYCLE) rst_n = 1'd1;
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#10 sysclk; = 1'd0;
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cpu_resetn = 1'd0;
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#(CYCLE) cpu_resetn = 1'd1;
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#(プログラムの実行サイクル数以上の数字) $finish;
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end
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endmodule
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