... | ... | @@ -190,11 +190,11 @@ BlockRAMの機能をフルに使うには、以下のように記述します。 |
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```verilog
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module databram(addr1, rdata1, we1, wdata1, addr2, rdata2, we2, wdata2, clk);
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input wire[13:0] addr1;
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output wire[31:0] rdata1;
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output reg [31:0] rdata1;
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input wire [3:0] we1;
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input wire[31:0] wdata1;
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input wire[13:0] addr2;
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output wire[31:0] rdata2;
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output reg [31:0] rdata2;
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input wire [3:0] we2;
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input wire[31:0] wdata2;
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input wire clk;
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... | ... | @@ -224,11 +224,11 @@ endmodule |
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```verilog
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module databram(addr1, rdata1, we1, wdata1, addr2, rdata2, we2, wdata2, clk);
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input wire[13:0] addr1;
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output wire[31:0] rdata1;
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output reg [31:0] rdata1;
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input wire [3:0] we1;
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input wire[31:0] wdata1;
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input wire[13:0] addr2;
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output wire[31:0] rdata2;
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output reg [31:0] rdata2;
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input wire [3:0] we2;
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input wire[31:0] wdata2;
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input wire clk;
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... | ... | @@ -267,11 +267,11 @@ endmodule |
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```verilog
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module databram(addr1, rdata1, we1, wdata1, addr2, rdata2, we2, wdata2, clk);
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input wire[13:0] addr1;
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output wire[31:0] rdata1;
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output reg [31:0] rdata1;
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input wire [3:0] we1;
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input wire[31:0] wdata1;
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input wire[13:0] addr2;
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output wire[31:0] rdata2;
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output reg [31:0] rdata2;
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input wire [3:0] we2;
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input wire[31:0] wdata2;
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input wire clk;
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... | ... | |